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A streaming validator that checks a UDP application payload's size and nested message boundaries before classifying its sequence range. Duplicates, overlaps, missing messages, and malformed packets each get an explicit outcome. A Python reference and a SystemVerilog implementation are tested independently and together.
FeedGuard checks a UDP application payload's size and nested message boundaries, then classifies its sequence range before advancing. Duplicates, overlaps, missing messages, and malformed packets each have an explicit outcome. A gap leaves the next expected sequence unchanged until the missing data is offered again. A Python reference and the SystemVerilog implementation are tested independently and together. The SystemVerilog datapath targets 10G/25G Ethernet/IPv4/UDP traffic on a 512-bit AXI-Stream bus, built in Xilinx Vivado and verified with cocotb. The walkthrough image replays eight recorded Python-reference packets. Tech stack: SystemVerilog, Python, AXI-Stream, Xilinx Vivado, cocotb
Developed in Xilinx Vivado and verified with cocotb.
64 cocotb tests; 322 MHz post-route.
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