An FPGA-based ground mission-control box for an experimental steerable-rocket research project. I'm building the digital logic, communication paths, and operator workflows that link the ground node to the vehicle during testing, and I verify them in simulation first. Testing is planned with the UMD Rocketry Club.

A low-cost drone and rover pair that share one ArduPilot control stack. The goal is to show that inexpensive off-the-shelf hardware can support coordinated autonomous operation in the air and on the ground. Current work covers tuning each vehicle, keeping telemetry in sync, and testing air-to-ground coordination.

A full-scale research vessel used as a shared test platform for sensors, mission computers, and communication links. I maintained its ArduPilot navigation stack and handled motor tuning, radar integration, and telemetry for the groups that relied on it. I also presented a proof of concept at a demo day.

A team-built autonomous vessel for mapping nitrate, oxygen, pH, and temperature across Chesapeake Bay. I worked on the ArduPilot/OpenPlotter navigation stack, sensor integration, and early neural-network models for dead-zone prediction. The project reached splash testing and helped secure a U.S. Coast Guard research grant.

A 32-GPU rig of NVIDIA RTX 3090 cards that I built in high school with my father and my cousin, then ran for five years. It taught me power distribution, thermal planning, and how to diagnose GPU failures under sustained load. With mining no longer profitable, I'm converting the hardware into an AI compute cluster.

Nexus is narb's edtech platform for schools, built at the AI startup I co-founded. It grew out of narbl, our earlier multi-LLM chatbot aggregator.

A React Native behavior-change app that I coded entirely for narb. It integrates a wearable API over OAuth, with background sync, local storage, and optimized geolocation. NoTestudo won the UMD xFoundry Oura Ring Challenge.

A remote FPGA controller for a Pong game. The player's client sends ball and paddle positions over an SSH tunnel to a relay on a friend's computer, and the FPGA controller returns a bounded paddle move over UART. The SystemVerilog controller has been demonstrated in simulation but hasn't run on FPGA hardware yet.

FPGA acquisition work for the SEDS@UMD GPS receiver, across the team's gps-rtl, gps-model, and fpga-utils repositories. The repository defines a board-neutral acquisition core and two development targets: a Basys 3 with a MAX2769 board over UART, and an STLV7325 Kintex-7 over Ethernet.

A streaming validator that checks a UDP application payload's size and nested message boundaries before classifying its sequence range. Duplicates, overlaps, missing messages, and malformed packets each get an explicit outcome. A Python reference and a SystemVerilog implementation are tested independently and together.