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FPGA acquisition work for the SEDS@UMD GPS receiver, across the team's gps-rtl, gps-model, and fpga-utils repositories. The repository defines a board-neutral acquisition core and two development targets: a Basys 3 with a MAX2769 board over UART, and an STLV7325 Kintex-7 over Ethernet.
I contribute to the SEDS@UMD avionics team's FPGA GPS receiver across the gps-rtl, gps-model, and fpga-utils repositories, using SpinalHDL, Python, and cocotb. The gps-rtl repository defines three targets: • GpsTop is a board-neutral serial-to-acquisition core with a result stream and an overflow diagnostic. It has no board wrapper or host transport yet. • uart_top targets a Basys 3 with a MAX2769 development board, for UART register control and sample capture. • eth_top targets an STLV7325 Kintex-7 board, for Ethernet acquisition development. LiteX scripts build the bitstreams, and each module is meant to have its own cocotb testbench. The images illustrate this intended integration. They aren't hardware photos or measured results. Tech stack: SpinalHDL, Python, cocotb, LiteX
Uses SpinalHDL, Python, and cocotb.
2,048-point FFT capture; 2.048 MSps acquisition; 24 cocotb benches.
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