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A remote FPGA controller for a Pong game. The player's client sends ball and paddle positions over an SSH tunnel to a relay on a friend's computer, and the FPGA controller returns a bounded paddle move over UART. The SystemVerilog controller has been demonstrated in simulation but hasn't run on FPGA hardware yet.
Rally is a remote controller for the included Pong game. The player runs the game and the Rally client on their own computer, with no FPGA, USB adapter, or other hardware attached. A friend runs a relay on their computer, which is connected to the FPGA over UART. The client sends ball and paddle positions over an SSH tunnel, and the FPGA returns a bounded paddle move. The relay only sends controller responses. It never pushes software to the player's machine, and only one player can use a relay at a time. Frames run at 115,200 baud with CRC and sequence checks and a 100 ms timeout. Status: the SystemVerilog controller has been demonstrated in simulation, and the image shows a recorded replay. A board wrapper for an Alibaba AS02MC04 card exists as a candidate, but it hasn't been compiled in Vivado or tested on a physical board. Tech stack: SystemVerilog, Python, Tk, pyserial, UART, SSH
Uses SystemVerilog and Python, with UART and TCP for communication.
CRC- and sequence-checked frames at 115,200 baud, with a 100 ms timeout.
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